What we can do for you
SIMPLEX simulations accurately predict the system performance of a complex system design by integrating real-time system performance on multiple interacting event timelines. Timelines are emulated for every component; processor timelines capture the task stream allocation, interrupts, preemption, and data accesses as well as periods of idle; bus timelines sequence message transmissions, segmentation, contention, gaps for the applicable protocol; data timelines profile usage exposing concurrent accesses; operator timelines show response delays and asynchronous command inputs. SIMPLEX synthesizes when and where activities take place as opposed to what activities do. SIMPLEX synthesizes how a system operates in time using parameters to characterize component runtimes, memory sizes, power consumption, throughput, bandwidth, etc. Overhead is characterized for interrupt detection, context switching, dispatching, message contention resolution, inter-message gaps, etc. Since SIMPLEX does not use actual code or actual hardware, we can simulate systems before code is written, or before the hardware is available.
Our models represent interfaces beyond just timing, signal, data, type and structure. These models represent measurement data by range, precision, accuracy, coordinate system, reference frame, and more. SIMPELX tools check all data interfaces for consistency and potential usage integrity hazards. SIMPLEX automatically incorporates full spectrum hazard protection into every simulation (patent pending).
Formal integration and testing time is substantially reduced because we identified and repaired many errors in the model before the problems are actually implemented. We literally model system integration which discovers and corrects timing errors, interface errors, loading, sequencing and integrity hazards long before physical integration and testing.
The simpleXecutive methodology and SIMPLEX tools can be applied at any phase of lifecycle. Processor and bandwidth utilization analysis reports quickly identify low-hanging fruit, bottlenecks, chokepoints and “easy stuff”. Our models can be easily changed and quickly simulated to show performance sensitivity which allows improved decision making prior to making a final design commitment.